LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY controlunit IS
	PORT(	instruction 	: IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
			MEM				: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
			WB, EX     		: OUT STD_LOGIC);
		 
END controlunit;
			
ARCHITECTURE behavior OF controlunit IS
	SIGNAL Opcode			: STD_LOGIC_VECTOR(3 DOWNTO 0);
	
BEGIN

	Opcode <= instruction(7 DOWNTO 4);

	-- Ula actions
	WITH Opcode SELECT
		EX <= 	'1' WHEN "0001",
				'1' WHEN "1011",
				'1' WHEN "0010",
				'1' WHEN "1100",
				'1' WHEN "0011",
				'1' WHEN "1101",
				'1' WHEN "0100",
				'0' WHEN OTHERS;
				
	-- Save in registers
	WITH Opcode SELECT
		WB <= 	'0' WHEN "1010",
				-- JUMPS:
				--'0' WHEN "1110",
				--'0' WHEN "1111",
				--'0' WHEN "0111",
				'1' WHEN OTHERS;
				
				
	-- "00" - nothing
	-- "01" - read
	-- "10" - write
	WITH Opcode SELECT
		MEM <= 	"00" WHEN "1000",
				"01" WHEN "1001",
				"01" WHEN "1110",
				"01" WHEN "1111",
				"10" WHEN "1010",
				"11" WHEN OTHERS;
				
END behavior;